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W25Q80BV
Table of Contents
1.
2.
3.
GENERAL DESCRIPTION ............................................................................................................... 5
FEATURES ....................................................................................................................................... 5
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Pin Configuration SOIC 150 / 208-mil .................................................................................. 6
Pad Configuration WSON 6x5-mm / USON 2x3-mm ........................................................... 6
Pin Configuration PDIP 300-mil............................................................................................ 7
Pin Description SOIC, WSON, USON & PDIP 300-mil ........................................................ 7
pin descriptions..................................................................................................................... 8
Chip Select (/CS) .................................................................................................................. 8
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 8
Write Protect (/WP)............................................................................................................... 8
HOLD (/HOLD) ..................................................................................................................... 8
Serial Clock (CLK) ................................................................................................................ 8
4.
5.
BLOCK DIAGRAM ............................................................................................................................ 9
FUNCTIONAL DESCRIPTION ....................................................................................................... 10
5.1
SPI OPERATIONS ............................................................................................................. 10
5.1.1
5.1.2
5.1.3
5.1.4
Standard SPI Instructions ..................................................................................................... 10
Dual SPI Instructions ............................................................................................................ 10
Quad SPI Instructions .......................................................................................................... 10
Hold Function ....................................................................................................................... 10
5.2
WRITE PROTECTION ....................................................................................................... 11
5.2.1
Write Protect Features ......................................................................................................... 11
6.
CONTROL AND STATUS REGISTERS ........................................................................................ 12
6.1
STATUS REGISTER .......................................................................................................... 12
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
BUSY ................................................................................................................................... 12
Write Enable Latch (WEL) .................................................................................................... 12
Block Protect Bits (BP2, BP1, BP0) ...................................................................................... 12
Top/Bottom Block Protect (TB) ............................................................................................. 12
Sector/Block Protect (SEC) .................................................................................................. 12
Complement Protect (CMP) ................................................................................................. 13
Status Register Protect (SRP1, SRP0) ................................................................................ 13
Erase/Program Suspend Status (SUS) ................................................................................ 13
Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 13
Quad Enable (QE) .............................................................................................................. 14
Status Register Memory Protection (CMP = 0)................................................................... 15
Status Register Memory Protection (CMP = 1)................................................................... 16
6.2
INSTRUCTIONS................................................................................................................. 17
6.2.1
Manufacturer and Device Identification ................................................................................ 17
-2-
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